I. Field of the Disclosure
The field of the disclosure relates to memory buffers, and particularly to dual-voltage domain asynchronous memory buffers.
II. Background
A memory buffer is a commonly used memory device to control data flow asynchronously. Data is stored in the memory buffer by a write device until ready to be streamed out of the memory buffer to a reading device. For example, a memory buffer may control flow of data sent from input/output (I/O) devices through universal asynchronous receivers/transmitters (UART) as a writing device to a central processing unit (CPU) as a reading device, or vice versa. A memory buffer may also be provided in other types of processors, such as digital signal processors (DSPs) for example. The memory buffer stores incoming data from the UART until the processor is ready to receive the data. The memory buffer streams the stored data received from the UART to the processor. For example, if the memory buffer is a FIFO memory buffer, the memory buffer streams the stored data out of the memory buffer in FIFO order. Other order schemes for streaming data may also be employed. Another example is a last-in, first-out (LIFO) data streaming order scheme. A memory buffer may also be employed to control flow of data from a processor to an I/O device. In this scenario, the memory buffer stores incoming data from the processor until the UART is ready to receive the data. The memory buffer streams the stored data received from the processor to the I/O device.
An example of a FIFO memory buffer 10 is illustrated in FIG. 1. As illustrated in FIG. 1, the FIFO memory buffer 10 includes a plurality of latch banks 12(0)-12(N−1) (wherein ‘N’ is a positive whole number such that the number of the plurality of latch banks is “N”). The latch banks 12(0)-12(N−1) may include flip-flop latch banks, labeled as “FFbank” in FIG. 1. The latch banks 12(0)-12(N−1) in this example are configured to hold data, such as a bit, byte, or word of data. A data input 14 is provided by a write device 16 to provide incoming data 18 to be written into one of the latch banks 12(0)-12(N−1) in the FIFO memory buffer 10. The write device 16 provides a write pointer 20 (WR_PTR) that provides a write address (WADDR) on a write pointer output 21 to select a specific latch bank 12(0)-12(N−1) into which the incoming data 18 is to be written.
With continuing reference to FIG. 1, the write device 16, the write pointer 20, and the latch banks 12(0)-12(N−1) are all clocked by a write clock signal 22. A read pointer 24 (RD_PTR) is provided by a read device 26 as a read address (WADDR) on a read multiplexor selector 28 into a read multiplexor 30 (READ_MUX). The read multiplexor 30 selects a specific latch output 32(0)-32(N−1) to read out data from a corresponding latch bank 12(0)-12(N−1). The data read out from the corresponding latch bank 12(0)-12(N−1) is provided as a latch data output 34 from the FIFO memory buffer 10 to be communicated to the read device 26. The read device 26 and the read pointer 24 are clocked by a read clock signal 36. The FIFO memory buffer 10 is an asynchronous memory buffer, because the write clock signal 22 clocking the write pointer 20 and the read clock signal 36 clocking the read pointer 24 are asynchronous to each other.
The FIFO memory buffer 10 in FIG. 1 can be configured to receive data from a CPU, DSP, or other processor write device to be written into the latch banks 12(0)-12(N−1). The data may be read out of the latch banks 12(0)-12)(N−1) by a read device, such as a UART provided in a semiconductor die 38 of an integrated circuit (IC) chip. For example, the CPU, DSP, or other processor may be provided as a core device in the semiconductor die 38. In this configuration, the processor is the write device 16, and the UART is the read device 26. Alternatively, the FIFO memory buffer 10 in FIG. 1 can be configured to receive data from a UART to be written into the latch banks 12(0)-12(N−1) and read out of the latch banks 12(0)-12(N−1) by a CPU. DSP, or other processor. In this configuration, the UART is the write device 16, and the processor is the read device 26.